Jeff Su: Okay. Thank you, Sunny. Operator, can we move on to the next participant.
Sunny Lin: Thank you very much.
Jeff Su: Thank you. Operator, can we move on to the next participant.
Operator: Sure. Our next question is come from Laura Chen with Citigroup. And Laura, please go ahead.
Laura Chen: Hello. Hi. Thank you very much for taking my questions. My first question is also about the overseas expansion. Like C. C. mentioned that the overseas more advanced than 20-nanometer, we account for 20% in the longer term perspective. And also, we are expanding more in the advancement in the U.S. I am just wondering that will you also expand more like second or the advanced packaging, along with your advanced now say like 5-nanometer or 3-nanometer in Arizona as well.
Jeff Su: Okay. So, Laura’s first question is actually, C. C. said the 20-nanometer below capacity could be 20% and more in several years’ time depending on customer demand and government support. But her question is, would we consider expanding advanced packaging overseas as well?
C. C. Wei: Well, today, we actually don’t have a plan, but we do not rule out the possibility because the back end is a part of the total wafer service for our customer, okay.
Laura Chen: Okay. Got it. And because we see that a lot of advanced now used for the high-computing PC, so along with that kind of application, we see now TSMC is very to that both 3D IC or the advanced packaging. So, I am just wondering that longer term perspective, whether that is also the direction in the U.S.
Jeff Su: So, I think what Laura is saying because, of course, that TSMC 3D IC solutions leading and HPC adoption is strong. So, with advanced technologies, will there be a need to build or have packaging in the U.S. as we move advanced technology portion to the U.S.?
C. C. Wei: Alright. Laura, I just answer that we don’t rule out the possibility. But today, we don’t have a plan yet.
Laura Chen: Sure. Thank you very much. And my second question is about the gain around roadmap. Can you give us more color on the current progress? We know that we have the schedule to ramping up in 2025 versus the EUV, the high-voltage equipment will probably only ready then. Do you think that could be any like potential pushback to like a 2026 onward?
Jeff Su: Okay. So, Laura’s second question is on the nanosheet transistor structure. She wants to know what is the progress for TSMC as we are adopting nanosheet structure at our N2. Will this be impacted or pushed out by the availability of things such as, I think you are asking high NA, Laura and things like that, correct?
Laura Chen: Right. Thank you.
C. C. Wei: Okay. Actually, our N2 technology development is on track, actually is better than what we thought. We have very good progress recently, and our risk production will be in 2024 and volume production in 2025. The schedule is not changed if we don’t put it in, but so far so good, let me assure you that.
Jeff Su: Okay.
Laura Chen: Okay. Thank you very much.
Jeff Su: Thank you, Laura. Operator, can we move on to the next participant, please.
