Synopsys, Inc. (NASDAQ:SNPS) Q4 2023 Earnings Call Transcript

Synopsys, Inc. (NASDAQ:SNPS) Q4 2023 Earnings Call Transcript November 29, 2023

Synopsys, Inc. beats earnings expectations. Reported EPS is $3.17, expectations were $3.04.

Operator: Ladies and gentlemen, welcome to the Synopsys Earnings Conference Call for the Fourth Quarter and Fiscal Year 2023. At this time, all participants are in a listen-only mode. [Operator Instructions] I would now like to turn the call over to Trey Campbell, Senior Vice President, Invest Relations. Please go ahead.

Trey Campbell: Thanks Lisa. Good afternoon everyone. With us today are Aart de Geus, Chair and CEO of Synopsys; Sassine Ghazi, President and COO; and Shelagh Glaser, CFO. Before we begin, I’d like to remind everyone that during the course of this conference call, Synopsys will discuss forecasts, targets, and other forward-looking statements regarding the company and its financial results. While these statements represent our best current judgment about future results and performance as of today, our actual results are subject to many risks and uncertainties. That could cause actual results to differ materially from what we expect. In addition to any risks that we highlight during this call, important factors that may affect our future results are described in our most recent SEC reports and today’s earnings press release.

In addition, we will refer to certain non-GAAP financial measures during the discussion. Reconciliations to their most directly comparable GAAP financial measures and supplemental financial information can be found in the earnings press release, financial supplement and 8-K that we released earlier today. All of these items, plus the most recent investor presentation, are available on our website at www.synopsys.com. In addition, the prepared remarks will be posted on our website at the conclusion of the call. With that, I’ll turn the call over to Aart de Geus.

Aart de Geus: Good afternoon. In Q4, we exceeded the high end of all our guidance targets and delivered another quarterly revenue high at $1.599 billion. Q4 thus capped a record year, growing revenue by 15% to $5.84 billion, with strong orders expanding backlog by $1.5 billion to $8.6 billion. We further improved non-GAAP operating margin to 35.1%, increased non-GAAP EPS by 26%, generated $1.7 billion in operating cash flow while maintaining an exceptionally strong balance sheet. Clearly, Synopsys has moved forward with sustained momentum. Over the last five years, we’ve grown revenue at 13% CAGR, expanded non-GAAP operating margin by 13 points, and increased non-GAAP EPS at a 23% CAGR. Through the year, we also widened our differentiation by substantially expanding our AI-driven product capabilities, but also through unique collaborations that strengthened our customers’ differentiation while cementing deep long-term relationships.

We thank our employees for their passion and dedication, and our customers for their business and trust in Synopsys. Meanwhile, dark geopolitical clouds are inflicting unimaginable harm in multiple conflict zones. Our hearts hurt with deep compassion for our employees, families, colleagues, customers, and all others impacted by pain, loss, and uncertainty. Yet, we will never give up believing in the positive potential of humanity. It is thus heartwarming to see how fast our teams have turned compassion into caring, caring into action, and how respect and support for each other is an active norm at Synopsys. Let me now briefly share some thoughts on the state of the industry and our company before I pass the baton to Sassine. From the first days of Synopsys 37 years ago, Synopsys has enabled and navigated the exponential ambition that came to be defining the semiconductor industry and which in turn radically impacted the world.

Our initial contribution, synthesis, revolutionized digital design. We ushered in the transition from CAD, Computer Aided Design, to EDA, Electronic Design Automation, so far delivering roughly a 10 million X increase in design productivity. During Synopsys’ entire existence, the vast majority of our products have been the state-of-the-art. Together with the leading foundries, we thus empowered digital age exponential, referred to as Moore’s Law. And then at the very moment that the economics of classic Moore’s Law are slowing down in terms of transistor performance and cost improvements, the era of big data and AI becomes real, triggering enormous compute needs on the horizon. About eight years ago, Synopsys forecasted this age of smart everything would become the driver for the semiconductor growth to a trillion dollars in this decade.

And here we are. This year’s Generative AI advances and furious adoption clearly fulfill our vision. As Pervasive AI is now massively underway, the classic Moore’s Law era in turn is morphing into the SysMoore era, systemic complexity but still with a Moore’s Law exponential ambition. SysMoore is happening in front of our eyes by reinventing architectures not based on a single chip, but on multiple chips, tightly connected, or even stacked on top of each other with extreme proximity. These so-called software-defined multi-die architectures will enable massive increases in the number of transistors available. And again, Synopsys is at the heart of the heart of catalyzing exponential impact. Our investments in multi-die design, our massive collection of IP building blocks in many silicon technology, our prototyping and electronic digital twinning technology that lets customers run software before the hardware actually exists, are all essential enablers driving the new race into AI driven computation.

Adding one more spark to our technical leadership, Synopsys also pioneered the use of DeepLearning.AI in chip design. Applied to optimization, verification, and test, production results are outstanding, and adoption is broad and rapid. Most recently, our announcement of exciting GenAI capabilities adds yet another angle to driving the state-of-the-art forward. If nothing else, my enthusiasm for both the CISMO opportunity and for our technology advances should give you a sense how Synopsys is on the move. Talking about on the move, we’re also well on the way in our executive leadership transition. I have great confidence, expectations, and enthusiasm for Sassine Ghazi as our next CEO. Sassine, please give us your perspective, vision and ambition for Synopsys.

The floor is all yours.

Sassine Ghazi: Thank you, Aart, for your pioneering work in our industry and for building Synopsys into one of the world’s essential semiconductor ecosystem companies. I am profoundly grateful for the opportunity to succeed you as CEO, building on our strong foundation and propelling Synopsys to the next wave of growth. Let’s turn to market trends. Despite global macroeconomic uncertainty, our customers continue to prioritize R&D investments and chip design starts remain robust. We leave 2023 with $8.6 billion in non-cancellable backlog, and have a time-tested business model that balances dynamic growth with macro resiliency. We expect solid growth across our geographies in 2024. But our outlook reflects a continued challenging near-term growth environment in China.

China is an adaptable and large market. However, given the combination of Entity List and technology restrictions and a weaker macroeconomic outlook, we believe more pragmatism in our 2024 China forecast is appropriate. Technology trends continue to create a rising tide for our business. Chief among those trends is a new era of AI driven productivity. AI is reshaping industries and providing breakthrough solutions for intractable challenges, like the 15% to 30% percent design resource shortage the semiconductor is facing this decade. We pioneered AI driven semiconductor design and are relentlessly advancing our AI capabilities so that we can drive step-up function improvement in our customers’ productivity and thus play a greater role in their success.

Recently, at Microsoft’s Ignite conference, we announced a breakthrough Generative AI capability for accelerating chip design, Synopsys.ai Copilot. The new capability is the result of a strategic collaboration with Microsoft to integrate Azure service that brings the power of GenAI into one of the most complex engineering challenges, the design process for semiconductors. The integration of GenAI across Synopsys.ai provides chip designers with collaborative capabilities that offer expert tool guidance, generative capabilities to enable RTL and collateral creation, and fully autonomous capabilities for workflow creation from natural language. We’re engaged with leading chip makers, including AMD, Intel, and Microsoft, to deliver the value of GenAI across the Synopsys.ai full EDA stack from design, verification, test to manufacturing.

We are at a very early stage of this new AI era, but our initial customer results are exceptional. AI is key to massively unlocking customer productivity, and we are increasing our investment to accelerate the Synopsys.ai roadmap. Beyond AI, we see multiple other secular tailwinds providing our design automation and Design IP business expanding growth opportunities. With the slowing of Moore’s Law, increasingly, architecture and design automation are the main levers in delivering semiconductor PPA gains, even as insatiable use case demands push the frontiers of performance and performance per watt. Multi-die implementations are accelerating as our customers seek to optimize cost and yield for these large complex designs. And our customers who rely on our critical competencies from silicon to software, now require a systems level approach, both at the semiconductor device level with multi-die and in the electronic design, software bring-up, and software validation of full systems, like today’s software defined cars.

Our Design IP business also has strong wind in its sails. Applications crave ever faster ingest and throughput, resulting in faster protocol migrations and increasing IP content value per device. Customers are prioritizing scarce design resources to focus on their critical architectural differentiation and turning to us as an integral part of their chip design development teams for their foundation and interface IP needs. And now, all three leading edge foundries are making Synopsys the advanced node IP vendor of choice. They are partnering with us on a broad range of IP titles to minimize risk and accelerate silicon success. Our design automation and Design IP businesses have both leadership technology and market positions with industry trends playing to our strengths.

We’re increasing our investment in these segments to capture more of this growing TAM. We started our investments in software integrity with the acquisition of Coverity in 2014. Software security was a pain point for every company, and risk surfaces were expanding. Customers were searching for innovative approaches in quality and security testing to help reduce the risk of software failures and security breaches. And we developed the broadest portfolio to meet that need. Flash forward to today, our software integrity business has become the leader in application security testing with industry leading team delivering over $0.5 billion in trailing 12 months revenue at mid-teens non-GAAP operating margin. We are proud of the significant progress we’ve made over the last nine years and believe the future opportunity remains attractive.

At the same time, we have compelling investment opportunities in design automation and Design IT with much higher expected growth and return profiles. Following our strategic portfolio review and in consultation with the company’s Board of Directors, we have decided to explore strategic alternatives for the software integrity business. As part of this process, we’re considering full range of strategic opportunities. We will provide an update after we conclude that process. Based on these market and technology trends and with high confidence in our business, here are our 2024 guidance targets. We expect 2024 revenue between $6.57 and $6.63 billion. We expect to deliver 37% non-GAAP operating margin, a 200 basis point improvement versus last year.

We expect full year non-GAAP EPS between $13.33 and $13.41. Shelagh will discuss the financials in more detail. Now I’ll share some segment highlights starting with design automation. This quarter, Synopsys.ai was selected by AspenCore to receive the World Electronics Achievement Award for EDA Software of the Year. We’re proud of the recognition, but even more excited by the strong customer adoption for Synopsys.ai across the design flow. A major North American hyperscaler made a major commitment to use DSO.ai after demonstrating PPA and productivity benefits on consecutive HPC projects. In verification, we engaged with over 20 customers in Q4, demonstrating up to 10x faster turnaround time. While in test, we added eight new customer engagements with [KIOXIA] (ph) publicly highlighting more than 50% pattern reduction.

Finally, we and TSMC announced that our analog migration flow through Synopsys.ai is enabled across TSMC’s advanced process technologies. We are also seeing great results deploying Synopsys.ai internally with our IP teams. Internal IP teams are seeing 10x turnaround time improvements in time to target verification coverage and have deployed analog design migration flows for TSMC 2 nanometer. Fusion Compiler continues to win key designs including the leading edge Arm mobile core for the industry’s first implementation for a gate-all-around based mobile SoC. In combination with DSO.ai, Fusion Compiler also delivered 10% better power on gate-all-around based mobile GPU and modem designs. We saw continued momentum in sign-off, delivered by our leadership family of prime tools.

We won multiple engagements with PrimeTime, PrimeClosure, and PrimeShield, and saw the world’s top three data center providers adopt PrimeClosure to get the fastest ECO closure time for five 3-nanometer SoCs. Expanding our multi-die ecosystem, we received the prestigious leadership award from TSMC, OIP 2023 Partner of the Year, for developing the industry’s first 3D IC design prototyping solution, supporting the new industry standard 3D blocks. Verification, product momentum also remains strong. This quarter, we announced our AI-driven next generation Verdi solution, which continues its lead in functional debug with deployment already at more than top semiconductor companies. In hardware assisted verification, we delivered another record year.

In Q4, ZeBu won against competition at two large North American hyperscalers, and we expanded our HAPS footprint with a large North American systems company and a large Asian semiconductor company. Now turning to Design IP. This quarter, we won our first 2-nanometer interface IP engagement with a leading mobile company and are now in production at 3 nanometer with foundation IP for a high-volume PC chip. We delivered a key multi-die proof point in concert with Intel and TSMC on UCIe interoperability. The demonstration at Intel Innovation showed die-to-die interconnect over UCIe between Synopsys IP on TSMC and 3E and Intel Foundry Silicon. We saw two other key technology proof points this quarter. We demonstrated interoperability for our 224 gig Ethernet PHY IP and PCIe 6.0 IP, both industry firsts.

On the processor IP side, we announced a new addition to the ARC processor IP portfolio, the RISC-V ARC-V processor IP. This product allows customers to choose from a broad range of flexible, extensible processor options that deliver optimal power performance efficiency for their target applications. Finally, we delivered a significant win in automotive, displacing competition at a marquee customer in a multi-generation, multiple project agreement. Now, to the software integrity segment, which delivered solid growth against the backdrop of continued macro headwinds for enterprise software. In Q4, we saw over 50% year-over-year growth in our Polaris software integrity platform. Polaris is a SaaS based application security testing solution optimized for the needs of development and DevSecOps teams.

We were also recently recognized as a leader in the Forrester Wave for Software Composition Analysis. This was based on an evaluation of Black Duck, our software composition analysis solution. In summary, we had an outstanding Q4 and FY 2023 financial results and operational execution and take tremendous forward momentum into 2024. We have a resilient business model and our customers continue to prioritize investments in the chips and systems that position them for future growth. We are aligning our portfolio investment with the greatest return potential to accelerate our growth, deepest thanks to our employees, partners, and customers for their passion and commitment. With that, I’ll turn it over to Shelagh.

Shelagh Glaser: Thank you, Sassine. 2023 was an excellent year highlighted by record revenue, record non-GAAP operating margin, and record earnings. We continue our strong execution with financial discipline and are confident in our business heading into 2024, driven by our execution and leadership position across our segment, robust chip and system design activity by our customers who continue to invest through semiconductor cycles and with $8.6 billion in non-cancellable backlog, the stability and resilience of our time-based business model. As a result, while the macro environment is uncertain. We expect to grow revenue 12.4% to 13.5%, expand non-GAAP operating margin by approximately 2 percentage points, and drive non-GAAP PPS growth of 19% to 20% in 2024.

Let me provide some highlights of our full year 2023 results. We generated total revenue of $5.84 billion, up 15% over the prior year, with double digit growth across all key products and geographies. Total GAAP costs and expenses were $4.6 billion and total non-GAAP costs and expenses were $3.8 billion, resulting in non-GAAP operating margin of 35.1%. GAAP earnings per share were $7.92 and non-GAAP earnings per share were $11.19, up 26% year-over-year. Now onto our segment. Design automation segment revenue was $3.78 billion, up 14% driven by strengths in EDA software and hardware. Design automation adjusted operating margin was 38.1%. Design IP segment revenue was $1.54 billion, up 17%, driven by broad-based strength. Design IP adjusted operating margin was 34.5%.

Software integrity revenue was $525 million, up 13%, and adjusted operating margin was 14.5%. Turning to cash. Operating cash flow for the year was $1.7 billion. We ended the year with cash and short-term investment of $1.59 billion and total debt of $18 million. During the year we completed buybacks of $1.2 billion or 80% of free cash. Now to targets which reflect the impact from export control regulations and assume no further changes for the year. Based on our current assessment of timing of hardware and IP deliveries, we expect the first half, second half split of approximately 48% to 52% for revenue and non-GAAP EPS. For fiscal year 2024, the full year targets are revenue of $6.57 billion to $6.63 billion, total GAAP costs and expenses between $5.0 billion and $5.05 billion, total non-GAAP cost and expenses between $4.14 billion and $4.18 billion, resulting in non-GAAP operating margin improvement of roughly 2 percentage points, non-GAAP tax rate of 15%, GAAP earnings of $9.07 to $9.25 per share, non-GAAP earnings of $13.33 to $13.41.

Cash flow from operations of approximately $1.4 billion, which includes an impact of approximately $200 million of 2023 taxes that we will pay in ‘24 and approximately $400 million of higher cash taxes due to the amortization of R&D expense. Following 2024, we expect cash tax growth rate to be approximately in line with operating income growth over a multi-year period. Now to targets for the first quarter, which includes an extra week compared to the first quarter of fiscal 2023. Revenue between $1.63 billion and $1.66 billion, which includes approximately $70 million from the extra week. Total GAAP cost and expenses between $1.22 billion and $1.24 billion, total non-GAAP cost and expenses between $1.02 billion and $1.03 billion, GAAP earnings of $2.40 to $2.50 per share, non-GAAP earnings of $3.40 to $3.45 per share, including approximately $0.14 from the extra week.

Our press release and financial supplement include additional targets and GAAP to non-GAAP reconciliation. I also want to highlight that we will be hosting our Investor Day on March 20th, which will be held in conjunction with our Synopsys Users Group event in Santa Clara. We look forward to seeing many of you there. In conclusion, we entered 2024 with momentum and confidence, reflecting our leadership position across our segments, robust design activity by our customers who continue to invest through semiconductor cycles, and the stability and resiliency of our time-based business line. With that, I’ll turn it over to the operator for questions.

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Q&A Session

Operator: Thank you. [Operator Instructions] We’ll take our first question from Harlan Sur with JP Morgan.

Harlan Sur: Good afternoon and congratulations on the strong execution and fiscal ‘24 guidance.

Aart de Geus: Thank you.

Harlan Sur: You’re welcome. Hardware verification, emulation, prototyping, I mean, this has been a big contributor to your double digits revenue growth profile over the past number of years. Lots of customers focusing on verification on these very complex chip designs, a lot of them wanting to get a head start on the embedded and application software development. Is the team anticipating another strong year next year for hardware? Will it be growing at a double-digit sort of growth rate within your fiscal ‘24 guidance? And if I look at inventories, right, they’re up 53% year-over-year to kind of record levels, which I think is a good indicator of a strong hardware pipeline, but wanted to get your views.

Sassine Ghazi: Yeah, thanks for the question. In terms of the need, exactly the way you highlighted it, the requirement to develop software early and having a hardware assisted verification to enable that step in the process is not only continuing, is accelerating with many system companies are trying to design their chip or even if they’re getting a chip from a semiconductor company, they want to start their software development and verification of the system early. And this is where our HAPS and ZeBu platform comes in to enable that part of the solution. We’re anticipating that to continue into 2024. As you saw as well, we had a record year for our hardware-assisted verification in ‘23, and we don’t anticipate anything different that will change going into 2024. As for the inventory comment, I’ll turn it to Shelagh for comments.

Shelagh Glaser: Sure, as Sassine said, we had a record in 2023. We expect another record in 2024, and we’re building inventory to be able to fulfill our customer demands.

Harlan Sur: Perfect. And maybe a similar question on your IP business, strong growth last year, right, up 17% going forward. I mean just continued tailwinds, right? Chip design complexity, driving more reliance on off-the-shelf IP licensing. And just as importantly, right, there’s some pretty big transitions on the interface and connectivity side, PCIe Gen 5, CXL, DDR5, HBM3e. Looking at your pipeline backlog, customer programs, will the IP business be growing slower, faster in line with the fiscal ’24 sort of total revenue profile?

Sassine Ghazi: So again, exactly the way you’re outlining the requirement, there is two factors. There’s the complexity and then there is the different methods of designing an SoC or chip with multi-die is opening up the door for new protocols, UCIE, the PCIe, the CXL, the one that you’ve listed. There are different protocols for various markets for automotive. As they expand their sophistication in developing the electronic system, it requires different requirements for the IP, interface IP for an automotive application. What we outlined in the script as well is today, we are the leading supplier for TSMC, Samsung and Intel Foundry business. And that puts us in a great position because most of these complex chip developments are on these advanced foundries.

And today, we are in a very fortunate position to be the partner and the leader in providing the IP for that business. So we expect that growth to continue, given the market demand for the sophisticated chips will continue.

Harlan Sur: Great insights. Thank you.

Sassine Ghazi: Thank you.

Operator: We will take our next question from Joe Vruwink with Baird.

Joe Vruwink: Great. Hi, everyone. I maybe want to start by parsing out some of the demand commentary. So first, there was a big step-up in backlog. I’d imagine that bodes well for 2024 and 2025 positive for revenue. At the same time, maybe the incremental moderation you’re signaling in China, as I think about just the last 12 months, I think China contributed about 2 points worth of revenue growth, just the incremental revenue contribution from China. So arriving at the 13% growth guidance, are you really seeing kind of good strength, something better than 13% and then China is maybe just a more neutral factor in your outlook?

Sassine Ghazi: We really took a balanced approach as we look at the guidance and the forecast for FY ’24. We took into account some of the headwinds that we’re seeing and of course, the number of the tailwinds that we are observing in the market. A couple of the headwinds, as we mentioned, one of them is China. And the two factors. One is the continued export restrictions and the other one that I’m sure all of you are observing, which is the macro economy inside China. The other headwind we took into account is the continued stress and pressure from enterprise software spending that does impact our software integrity business. From tailwinds, and this is where we get excited about is exactly what we’re seeing, the AI as a megatrend is driving amazing silicon demand and that silicon demand is complex.

It’s on the most advanced nodes and it’s giving us an amazing opportunity for our design automation and design IP. So as we took into account the both headwinds and the tailwinds. We came with a balanced view of the guidance around 13% midpoint for FY ’24.