Kevin Cassidy: Congratulations on the good results and congratulations also for introducing the third generation DDR5. And as you’re speaking with your customers, do you have an idea of what the bell curve or what the distribution will be for each one of those speed ranges, Gen 1 through Gen 3?
Luc Seraphin: Thank you, Kevin. The qualification cycles for the RCD chips are quite long and complex, and they’re based on the performance of the chips, they are based on interoperability between the memory and the processors and signal integrity. And to give you a little bit of background, the DDR5 ramp that will happen this year — that is happening this year on the Sapphire Rapids and general platform is based on our Gen 1 RCD, which we announced in September of ’17. The second generation of RCD, we announced it in October ’21, some time ago, and that will address the follow-on products, which will be introduced to the market in 2024. And the third generation, which we just announced right now on 5,400 mega transfers per second is going to address, again, the following generation that will be introduced in the market of 2025.
It’s always very important for us to be ahead of the market to engage with the ecosystem to go through these very complex qualification processes with our customers so that we continue to grow our share as we move. So this year, Generation 1 of our RCD is going to be the one in production, Generation 2 will start to be in production next year and Generation 3, which we just announced, will start to be in production in 2025.
Kevin Cassidy: I see. Very clear. And maybe if you could give us the status of your — the other chips that are going on to a DDR5, the temperature controller, the SPD hub, just an update on the status of those devices.
Luc Seraphin: Yes. So we announced the SPD hub and the temperature sensor in July of last year. We’re well ahead with the qualification with our customers, as we speak, and we expect those products to start generating revenue towards the end of this year. That’s where we are, at the same status as last quarter.
Operator: The next question comes from the line of Mehdi Hosseini of SIG.
Mehdi Hosseini: One for Luc and one follow-up for Des. I just want to go back to the silicon IP and I wanted to understand how the mix would change, especially as we migrate from the first half to the second half. Would there be opportunity with the CXL 2.0, where you can actually use the existing DIMM slot to — as a DDR4? Would that create kind of opportunity for you, especially with the CXL 2.0 and memory controller? And I have a follow-up.
Luc Seraphin: Thank you, Mehdi. So when it comes to CXL, we have introduced last year a series of IPs that address the CXL market. We announced our CXL 2.0 IP in January of last year. We announced CXL 3.0 towards the end of the year as well as PCIe Gen 6. So we continue to have design wins in the CXL space with SoC vendors that build SoCs for the CXL market. The CXL market will start in earnest towards the end of next year. That’s where, for us, we’re going to start to see product revenue. So from an IP standpoint, as we said, the view we have on our IP business this year is that it’s going to grow in aggregate low to mid-single digits because a lot of the design slots has been accessed at this point in time. Given the economic environment, we do see a slight slowdown of design starts, but CXL will start.
