And when Doug just talked about spending, I mean, I’ve tried to lay out for you in the last several quarters, the breadth of opportunities that are ahead of the company, many of which — not all, but many of which are on the foundry logic side. I mean just to kind of recap some of those, I mean, the dry EUV photoresist and develop. When we said that’s $1.5 billion opportunity over five years. And when you get towards the tail end of that five years, I mean, that’s a revenue that’s growing with the number of expanding EUV layers at every technology node after that. That’s primarily foundry logic business. We talked about gate all around, about $1 billion incremental opportunity for Lam introduces opportunities to win new tools and selective etch and ALD.
And so that’s same expansion for us in foundry logic and opportunity to grow. We talked about advanced packaging. I mean you’ve already seen what’s happened with not only the HBM side of AI, but also the entire formation of these big AI systems using interposers. Lam’s invested now in panel processing as a way to ultimately bring down the costs of some of this chiplet — these chiplet applications. And then finally, today, I just talked about backside power distribution as a new way of being very creative about how you use that backside of the wafer is additional real estate and it opens up a lot of new opportunities for us, and that’s primarily a foundry logic application as well. And so really, what we’re talking about is Lam has a long way to go to expand our SAM, especially on the foundry logic side.
That’s what we’re investing for. And each of these is a $1 billion-plus opportunity for Lam over the next several years. And so we’re pretty excited about that. But we’re not giving up on our strong memory positions.
Srinivas Pajjuri: Thank you. I appreciate that answer. And then my quick follow-up on the HBM, I guess, technology itself. A lot of questions have been asked already. Just on the capital intensity of HBM. Tim, I mean, I know you said the die size is larger and I guess, cycle times are longer, et cetera. But is there a way to think about capital intensity per wafer or per bit? How we should think about HBM versus traditional DDR?
Tim Archer: Well, I think it’s a — I don’t know that we’ve quantified that number, but it’s — it obviously is a much higher performance die than our device, and it does — it is bigger and takes more capital. And so therefore, it’s a performance-driven application. From our perspective, though, what really is interesting is that, many of the new tools that get added to enable HBM or Lam tools or tools that are in our market, things like silicon etch and copper plating for the TSV formation. And so that’s what really makes it an even better transition for [indiscernible] company like Lam.
Srinivas Pajjuri: Got it. Thanks, Tim.
Tim Archer: Thanks, Sri.
Operator: And our next question today comes from Brian Chin with Stifel. Please go ahead.
Brian Chin: Good afternoon. Thanks for letting us ask a few questions. So about a week ago, the U.S. relaxed its licensing requirements for some foreign companies that operate more advanced fabs in China. I know it’s fairly recent, but have you seen a positive impact yet from this change in the licensing policy. I did note that in talking about China remaining a good concentration in the December quarter. It sounds like maybe there could be some shifting there between local and maybe foreign domiciled companies?
Tim Archer: Yes. It’s pretty — that comment is pretty recent. But I think relative to multinationals, wherever they operate, whether China or certainty of being able to make the investment and benefit from that long term is very important. So obviously, in the last couple of weeks, we haven’t seen any movement that we had talked about. I think long term, it allows people — it allows our customers to ultimately make the right decisions for them about where to invest. And that is especially true when you think about our installed base and the upgrades to the installed base and a customer willingness to sort of move forward with those upgrades with certainties.
Brian Chin: Got it. That’s helpful. And then a lot of questions have been asked about sort of service spares and utilization improvements. But just curious, if memory companies are kind of talking as is they’ll realize some of that utilization improvement, not just through increasing wafer starts, but also through some reduction in wafer start capacity as they emphasize newer nodes or capital efficiencies on some wafer loss there. How are you thinking about how that impacts maybe the trajectory of your service and spares revenue growth in calendar 2024?
Tim Archer: Well, I think that we have to see and we — as we said about the — it’s difficult to predict the pace of the recovery. But what happens there is we’re just trading off 1 part of our business that CSBG business for another. If upgrades happened before spares, you’re right, it brings utilization down. But there’s also something that we’ve said, which is as technology moves forward, many of those applications become more spares intensive because the processes are longer and more demanding. And so I would just say that we’re going to see a rise in both parts of our business as fab operations recover and customers start to fully utilize the equipment in those fabs.
Operator: Thank you. And our next question today comes from Mehdi Hosseini with [SIG] (ph). Please go ahead.
Unidentified Analyst: Yes. Thanks for taking my question. Just two quick follow-ups. Opportunities with the back side power rate. Should I think about it more of a 3-nanometer or extension of 3-nanometer? Or are those opportunities materializing when we migrate to 2-nanometer. And I have a follow-up.
