Charles Shi: Thanks, Mike. I really appreciate the usual conservatism. But maybe a follow-up. In terms of HBM, if I remember correctly, probably second half last year, it’s mainly driven by primary loan customer. Did you see a broadening of the demand and maybe you’re seeing to customer demand right now? And specifically, I want to ask, we did hear chapters about the second one, not the leader, but the one follower having some yield issues. Is that reflected in probably higher propane (ph) in the short-term or you don’t see that as an issue? Thanks.
Mike Slessor: Yeah. Our HBM business is still relatively concentrated with one customer, although there are contributions from the other two DRAM manufacturers as they quickly sample and start to ramp HBM3 and HBM3E here in 2024. We would expect, that market to broaden a little bit. But at present and with the visibility we have, it really is continue to be driven and pretty concentrated by the leader in HBM market share. I think it’d be interesting to see as we go through the back half of the year and all three start to supply HBM3 in volume and then transition in 2025 to HBM4. We expect that business to broaden quite significantly and be a supplier to all three of them. But again, pretty concentrated with one customer right now.
Charles Shi: Thanks, Mike. I really congrats on the very strong guidance. Thanks.
Operator: Thank you. One moment for our next question. And our next question comes from the line of David Duley from Steelhead Securities. Your question, please.
David Duley: Congratulations on great results. I just had a couple of follow-up questions on the high-bandwidth memory market. You did a great job of talking about the number of insertions. I was just wondering if you could kind of just quickly review two things. If you could just tell us how much you think high bandwidth memory, how much more test and probe intensive it is over, let’s say, a standard DDR5 memory? And then could you just review, it sounds like you have with the six, if you have eight in the stack, you’re going to have at least eight probe insertions for each individual one. How many more insert or how many more probe or testings are they when you build the stack? Thank you.
Mike Slessor: Yes. Thanks, David. A couple of things. Your math is correct. Each individual die, whether it’s a 8-high stack, a 12-high stack, a 16-stack, each of those individual die gets probed and tested, before it goes into the stack, because as you can imagine, especially when you get high in the stack, if you’re adding a bad dye to it, that has the potential to essentially cause a scrap event for all the previous die that have been stacked. So the notion of known good die for each of these input die is something we are seeing. There’s also, for sure, a test once the thing is completely stacked, and that often happens at high speeds, and I reference some of the challenging thermal specifications. And at least for the initial parts of HBM ramps, we’re also seeing intermediate test insertions as the stack is built.
You can imagine there’s — suppose you get the four high, there can be a test insertion there, depending on what yield low yield loss modes the customers are seeing. There’s been all kinds of challenges associated with HBM. It’s driven results for some of the metrology and inspection suppliers in the back end as well as customers try and uncover these new yield modes, yield loss modes and improve them and drive. But for right now, we’re seeing all the input die get tested, each of the component die get tested, a test at the end, and often, some intermediate tests as it’s stacked up.
David Duley: And then just the testing intensity of an HBM dive versus a standard DDR5?
Mike Slessor: Yes. We’ve estimated this in the past. On a like-for-like basis is something like 20% to 30% and I think that’s a reasonable rule of thumb and continues to be a reasonable rule of thumb. There are situations, where the test intensity is higher than 20% to 30%. Often, if it’s a new product or when you’re moving from 12 high to 16 high, new defect modes appear that need to be maybe over tested compared to that 20% to 30%. But I think that remains a pretty good rule of thumb for the uplift associated with advanced packaging chips on a like-for-like basis.
David Duley: Okay. If I could just look at a follow-up here, as far as your foundry and logic business, it’s great to see a nice build-up. Do you think you’ve increased your market share or is that just what your big running customers inside these two big customers are kind of have?
Mike Slessor: Yes. So a couple of points on share. We and I think most of the people who follow the industry rely on the tech insights, the formerly VLSI research report, that should be out any day now, for 2023. So that’ll be the definitive word on market share. Having said that, as you can imagine, we do some pretty high-frequency internal benchmarking and data collection. And based on that, we do believe we’ve grown share, through 2023, not just in Foundry & Logic, but in our other served markets as well. As we talked about with you in the past, share gains and market leadership is a real core tenant of our long-term strategy and we need to continue to drive share gains.
David Duley: Thank you.
Operator: Thank you. One moment for our next question. And our next question comes from the line of Craig Ellis from B. Riley Securities. Your question, please.
Craig Ellis: Yeah, thanks for taking the question and congratulations on the very good execution. Mike, I’ve just joined the party and ask one on high bandwidth memory and maybe I’ll position it this way. It looks like in 2Q, we should be at around $30 million in quarterly revenues and as I’ve listened to some of your commentary, and look at the different times we’re probing die, add input, intermediate steps, final stack, et cetera. Is there anything that you see, as we look out from high bandwidth memory 3 to 3E to 4 that would cause, probe intensity to go down? And if so, what would that be and what would be either the yield improvement or the other process improvements that a manufacturer might make to achieve that?
Mike Slessor: Yeah, It’s an interesting question, Craig. As you go from 3 to 3E to 4, especially the 3 generation to 4. There’s a couple of things that are really increasing the probe card intensity and complexity. One is, generally, the transitions involve more die stacked. And so as we talked about, each of the component die gets probed. And so you can imagine more component die in a higher stack is going to drive, higher test intensity for the finished part. I think the other piece certainly going from 3 to 4, there’s a significant step up in speed. And that’s one of the areas, where FormFactor has a very differentiated set of DRAM products in delivering high-speed test to screen out die, that don’t meet the speed standard to participate in the whole stack at the spec speed for something like an HBM 416 high-stack.
